1. Field of the Invention
This invention relates to a CMOS semiconductor integrated circuit device with a multilayer wiring structure, and more particularly to a pattern layout of power-supply lines used in a unit functional block composed of identical blocks arranged repeatedly, such as data paths.
2. Description of the Related Art
FIGS. 1A and 1B show the circuit schematic and pattern layout of an ordinary CMOS n-input NAND circuit as a basic cell used in a CMOS semiconductor integrated circuit device with a multilayer wiring structure. As shown in FIG. 1A, the current paths of p-channel transistors P1 through Pn, the individual gates of which receive input signals S1 through Sn, respectively, are connected in parallel between the power supply v.sub.cc and the output node ND. The current paths of n-channel transistors N1 through Nn, the individual gates of which receive input signals S1 through Sn, respectively, are connected in series between the output node ND and the ground point V.sub.ss.
As shown in FIG. 1B, the gate lines G1 through Gn respectively receiving the input signals S1 through Sn are formed longitudinally, being separate from each other. These gate lines G1 through Gn are shared by the transistors whose gates receive the same signal: transistors P1 and N1, transistors P2 and N2, . . . , transistors Pn and Nn. The drain and source regions 71 of each of the transistors P1 through Pn are formed in the semiconductor bodies (the n-type semiconductor substrate or the n-well regions) on both sides of each of the gate lines G1 through Gn. The drain common line 72 is formed so as to cross the gate lines G1 through Gn at right angles (in the lateral direction), and is connected to the individual drain regions of the transistors P1 through Pn. Interposed between the drain common line 72 and the semiconductor body is an insulating film (not shown), in which contact holes are formed, through which the line 72 is electrically connected to each drain region. The source and drain regions 73 of each of the transistors N1 through Nn is formed in the semiconductor bodies (the p-well regions or the p-type semiconductor substrate) on both sides of each of the gate lines G1 through Gn, separately from the region 71. The output line 74 of the NAND circuit is connected to both the drain common line 72 and the drain region of the transistor Nn. The power lines (the V.sub.DD line and V.sub.SS line) 75 and 76 are formed laterally or in the direction of channel length of individual transistors P1 through Pn and N1 through Nn, separately from each other. The V.sub.DD line 75 is electrically connected to the individual source regions of transistors P1 through Pn. The V.sub.SS line 76 is electrically connected to the source region of transistor N1.
For such basic cells, the circuit pattern height (the longitudinal length) and the power supply pattern width are standardized so as to allow other basic cells to be formed immediately next to a basic cell on both sides.
FIGS. 2A and 2B show the circuit schematic and the pattern layout of a CMOS composite gate circuit essential for higher integration and faster speed, as another example of a conventional basic cell. This circuit is composed of p-channel transistors P1 through P4, whose gates receive input signal S1 through S4, respectively, and n-channel transistors N1 through N4, whose gates receive input signal S1 through S4, respectively. The current paths of transistors P1 and P2 are connected in parallel between the power supply V.sub.cc and the node Pa, while the current paths of transistors P3 and P4 are connected in parallel between the node Pa and the output node ND. The current paths of transistors N2 and N1 are connected in series between the output node ND and the ground point V.sub.ss. Similarly, the current paths of transistors N3 and N4 are connected in series between the node ND and the point V.sub.ss.
As shown in FIG. 2B, the gate lines G1 through G4 receiving input signals Sl through S4 are formed longitudinally, being separate from each other. These gate lines G1 through G4 are shared by the transistors whose gates receive the same signal: transistors P1 and N1, transistors P2 and N2, . . . , transistors P4 and N4. The drain and source regions 81 of each of the transistors P1 through P4 are formed in the semiconductor bodies (the n-type semiconductor substrate or the n-well regions) on both sides of each of the gate lines G1 through G4. The intermediate connection line 82 of the transistor portion is formed so as to meet the gate lines G1 through Gn at right angles (laterally), and is connected to the drain regions of transistors P1 and P2 and to the source regions of transistors P3 and P4. Interposed between the intermediate connection line 82 and the semiconductor bodies is an insulating film (not shown), in which contact holes are formed, through which the line 82 is electrically connected to each of the drain and source regions. The source and drain regions 83 of each of n-channel transistors N1 through N4 are formed in the semiconductor bodies (the p-well regions or the p-type semiconductor substrate) on both sides of each of the gate lines G1 through G4, separately from the region 81. The output line 84 of the composite gate 84 is connected to both the common drain region of transistors P3 and P4 and the common drain region of transistors N2 and N3. The power lines (the V.sub.DD line 85 and V.sub.SS line 86) are formed laterally or in the direction of channel length of individual transistors P1 through P4 and N1 through N4. The V.sub.DD line 85 is connected to the source regions of transistors P1 and P2, while the V.sub.SS line 86 is connected to the source regions of transistors N1 and N4.
However, a basic cell with the pattern layout as shown in FIG. 2B has many unused spaces or wasted 87 under and near the power lines 85 and 86. As composite gates are used more positively, a smaller percentage of the transistors used are directly supplied with power, resulting in more dead spaces 87. For a basic cell with the above structure, although in some cases, the transistor width may be narrowed for higher integration on the basis of the calculated loads for the intermediate connection points Pa, Na, and Nb, the restrictions due to the power supply lines prevent the pattern area from being minimized. In other words, conventional pattern layouts for power lines are unsuitable for positive use of composite gates.
In a layout of a data path system using multilayer wiring CMOS semiconductor integrated circuit devices, the width of each basic cell is kept constant and circuit patterns or different basic cells are arranged in the longitudinal direction in which data is transferred. Further, the pattern of the longitudinally arranged circuit blocks is repeated in the lateral direction, with a common control signal wiring pattern and a power supply wiring pattern being provided for those laterally repeated identical basic cells. These wiring patterns are formed of layers below the layer to which the power lines belong.
In a data path system where data flows with regularity and the direction of data transfer is at right angles to the direction of control signal transfer, the identical basic cells repeated laterally are switched at the same time. In this case, if a power supply line with a constant width is shared by the laterally repeated basic cells, noise is liable to be induced on the power line at the moment of simultaneous switching.
FIGS. 3A and 3B show the input-to-output transfer characteristics and the direct-current characteristics in a transitional state for a CMOS inverter used as a basic cell. Since in the transient state II, a large current (ranging from several tens to several hundreds of uA) flows compared to the high level output state I and the low level output state III, it is understood that noise is liable to be induced on the power lines.
To restrain noise from occurring, the power lines are widened or a circuit block with a special noise preventive pattern is provided. The former measure, however, increases unused spaces, which imposes more restrictions on pattern formation in standardizing power supply wiring, lowering the flexibility in pattern design. The latter complicates the pattern layout, making it more difficult to use a CAD (Computer-Aided Design) device for automatic pattern generation.
As described above, the pattern layout of the power supply wiring in a conventional semiconductor integrated device is unsuitable for positive use of composite gates, because the formation of composite gate circuits leads to many unused spaces. Further, since the gates are formed in the direction perpendicular to the direction of regular signal flow peculiar to a data path system, noise is liable to be induced on the power supply lines at the moment of simultaneous switching. To cope with this noise problem, more restrictions must be placed on pattern formation in standardizing power supply wiring, which causes many drawbacks, including the decreased flexibility in pattern design and a complicated pattern layout that makes automatic pattern generation by a CAD device more difficult.